A CMUT on CMOS imaging chip is disclosed. The imaging chip can use direct connection, CMOS architecture to minimize external connections and minimize chip cross-section. The CMOS architecture can enable substantially the entire chip area to be utilized for element placement. The chip can utilize arbitrarily selected transmit (Tx) and receive (Rx) element arrays to improve image quality, while reducing sampling time. The chip can comprise a plurality of dummy elements dispersed throughout the Tx and Rx elements to reduce cross-talk. The chip can utilize batch firing techniques to increase transmit power using sparse Tx arrays. The chip can comprise hexagonal Tx and or Rx subarrays for improved image quality with reduce sample sizes. The chip can utilize electrode geometry, bias voltage, and polarity to create phased and amplitude apodized arrays of Tx and Rx elements.
