An imaging system detector array (112) includes a detector tile (116). The detector tile includes a photosensor array (202), including a plurality of photosensor pixels (204). The detector tile further includes a scintillator array (212) optically coupled to the photosensor array. The detector tile further includes an electronics layer or ASIC on a substrate (214) that is electrically coupled to the photosensor array. The electronics layer includes a plurality of individual and divisible processing regions (302). Each processing region including a predetermined number of channels corresponding to a sub-set of the plurality of photosensor pixels. The processing regions are in electrical communication with each other. Each processing region includes its own electrical reference and bias circuitry (802, 804).
