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TRIM METHOD FOR PATTERNING DURING VARIOUS STAGES OF AN INTEGRATION SCHEME
专利权人:
Tokyo Electron Limited
发明人:
Raley Angelique,Ko Akiteru
申请号:
US201715445042
公开号:
US2017256395(A1)
申请日:
2017.02.28
申请国别(地区):
美国
年份:
2017
代理人:
摘要:
Provided is a method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising: providing a substrate in a process chamber of a patterning system, the substrate comprising a first structure pattern and an underlying layer, the underlying layer comprising a silicon anti-reflective coating (SiARC) or a silicon oxynitride (SiON) layer, an optical planarization layer, and a target patterning layer; performing an optional CD trimming process of the first structure pattern; performing a series of processes to open the SiARC or SiON layer and performing additional CD trimming if required; and performing a series of processes to open the optical planarization layer, the series of processes generating a final structure pattern, and performing additional CD trimming if required; wherein the planarization layer is one of a group comprising an advance patterning film (APL), an organic dielectric layer (ODL) or a spin-on hardmask (SOH) layer.
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中国工程科技知识中心
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