Low power high performance electrical circuits

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专利权人:

Shau Jeng-Jye

发明人:

Shau Jeng-Jye

申请号：

US201615236327

公开号：

US9632571(B1)

申请日:

2016.08.12

申请国别(地区):

美国

年份:

2017

代理人:

摘要：

A power saving mode especially useful for memory decoders has been developed. At this power saving mode, the drain-to-source voltage of every MOS transistor in a memory decoder is set to zero, while at normal operation the memory decoder supports the same functions as prior art memory decoders.

来源网站：

中国工程科技知识中心

来源网址：

http://www.ckcest.cn/home/