Techniques for processing instructions include receiving a plurality of instructions from a program counter (PC) operable to be fused into a PC-relative plus offset instruction. The technique also includes fusing the plurality of instructions into an internal operation (IOP) that specifies PC-relative addressing with an offset. The technique also includes computing a shared PC portion that includes one or more common upper bits of a PC address of each of the plurality of instructions. If the shared PC portion is different than a previously computed shared PC portion, the technique transmits the shared PC portion to one or more downstream components in the processor pipeline. The technique further includes transmitting the IOP with a representation of lower order bits of the PC address and processing the IOP.
