Ray Joydeep,George Varghese,Sodhi Inder M.,Wilcox Jeffrey R.
申请号：
US201314140261
公开号：
US9600413(B2)
申请日:
2013.12.24
申请国别(地区):
美国
年份:
2017
代理人:
Lowenstein Sandler LLP
摘要：
Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.
