FOUNDATION FOR RESEARCH & BUSINESS, SEOUL NATIONAL UNIVERSITY OF SCIENCE & TECHNOLOGY
发明人:
Lee Seung Eun,Jeong Yeong Seob,Lee Seong Mo
申请号：
US201414585982
公开号：
US9671447(B2)
申请日:
2014.12.30
申请国别(地区):
美国
年份:
2017
代理人:
Harness, Dickey & Pierce, P.L.C.
摘要：
In order to improve reliability of a system-on-chip (SoC) through fault tolerance verification, there is provided a method of analyzing an error rate in a system-on-chip (SoC) having at least one internal block obtained by interconnecting two or more gates, comprising: applying an input signal to an input terminal of a certain internal block; defining an input error rate of each gate of the internal block; and defining an output error rate of the internal block based on the input error rate of each gate and an error rate propagating to an output terminal. As a result, there is proposed a method of analyzing a change of the output error rate depending on the input error rate in a gate level in error model development necessary to design and verify a fault-tolerant SoC. Therefore, it is possible to analyze errors in each gate and formularize error rate information modeling including an input/output relationship between each gate of a digital circuit in a library form.
