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高密度チップ間接続
专利权人:
インテル アイピー コーポレイション
发明人:
トルシュテン メイヤー
申请号:
JP20150126181
公开号:
JP6275670(B2)
申请日:
2015.06.24
申请国别(地区):
日本
年份:
2018
代理人:
摘要:
An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads and top surfaces of the first and second IC dice include a second plurality of connection pads. The apparatus also includes a layer of non-conductive material covering the top surfaces of the first and second IC dice, a plurality of through-vias, first conductive interconnect between at least a portion of the first plurality of connection pads and at least one through via, and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

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