JHA Praket P.,KO Allen,HAN Xinhai,KWON Thomas Jongwan,KIM Bok Hoen,KIL Byung Ho,KIM Ryeun,KIM Sang Hyuk
申请号：
US201615063569
公开号：
US2016293609(A1)
申请日:
2016.03.08
申请国别(地区):
美国
年份:
2016
代理人:
摘要：
Implementations of the present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.
