Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor
Bradbury Jonathan D.,Gschwind Michael Karl,Schwarz Eric M.,Shum Chung-Lung K.,Slegel Timothy J.
申请号：
US201514825264
公开号：
US9740615(B2)
申请日:
2015.08.13
申请国别(地区):
美国
年份:
2017
代理人:
Zwick David
摘要：
Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by the processor. The processor executes a transactional memory (TM) transaction, including receiving, by the processor, a memory address range of data that a co-processor may access to perform a co-processor operation. The processor saves the memory address range. Based on receiving, by the processor, a cache coherency request that conflicts with the saved address range, the processor aborts the TM transaction.
