A computing device with multi-layer control: mentor layer and instruction/control layer includes a memory and one or more functional units. The computing device is configured to implement a multi-layer control structure including a data structure layer including a local high speed memory, a mentor layer, and an instruction/control layer. The local high speed memory includes one or more variables. The mentor layer includes one or more mentor circuits. The mentor circuits control actions associated with the Variables in the local high speed memory. The instruction/control layer includes one or more control circuits that interpret instructions or control operations by one or more functional units. In some embodiments, the local high speed memory implements a frame/bins structure. In some embodiments plural information is included in HLL and/or machine language.
