A latch circuit, a receiver circuit, a semiconductor apparatus, or a system may be provided. The latch circuit may include a delay configured to delay an input signal and generate a delay signal. The latch circuit may include a control signal generator configured to enable a control signal based on the input signal and the delay signal, and disable the control signal based on a reset signal. The latch circuit may include a gating circuit configured to output, based on the control signal, the input signal and the delay signal to an output node. The latch circuit may include a latch configured to latch, based on a strobe pulse, an output of the gating circuit and generate an output signal.
