COMPUTATION CIRCUIT, ENCODING CIRCUIT, AND DECODING CIRCUIT

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专利权人:

Fujitsu Limited

发明人:

TOMITA, Yoshinori

申请号：

EP20140892478

公开号：

EP3148092(A4)

申请日:

2014.05.23

申请国别(地区):

欧洲专利局

年份:

2017

代理人:

摘要：

In order to speed up computation processing, memories (M0 to M15) retain data blocks on which exclusive logical OR computation is performed, and selection circuits (2a to 2p) receive a selection signal and select two or more data blocks for use in exclusive logical OR computation from among a plurality of data blocks read from the memories (M0 to M15) on the basis of the selection signal, and XOR circuits (3a to 3o) (exclusive logical OR computation circuits) perform exclusive logical OR computation based on the two or more data blocks selected by the selection circuits (2a to 2p).

来源网站：

中国工程科技知识中心

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http://www.ckcest.cn/home/