Dreps Daniel M.,Franz Keenan W.,Pham Nam H.,Walls Lloyd A.
申请号：
US201614989553
公开号：
US9536604(B1)
申请日:
2016.01.06
申请国别(地区):
美国
年份:
2017
代理人:
Patterson + Sheridan, LLP
摘要：
A memory system is deigned for impedance matching using a network of resistors that are tuned to reduce reflections on a shared bus. Any deviation from the matched state causes a mismatch and results in reflections on the bus. Overall signal reflections are reduced by balancing the back reflections occurring at a connector junction coupled to a pair of resistors and the back reflections occurring at the input of the DIMMs. This balance or tradeoff is achieved by changing the resistance value of the resistor pair to reduce the overall back reflections in the memory system.
