PROBLEM TO BE SOLVED: To provide a multiphase clock generation circuit and a DLL circuit therewith which can generate a plurality of clock signals different in phase in response to a reference clock signal even if the reference clock signal is a high speed one.SOLUTION: Each delay circuit of a delay circuit group of n cascaded delay circuits for outputting clock signals different in phase via a delay signal line feeds a charging current to the delay signal line or draws a discharging current greater than the charging current from the delay signal line, in response to a clock signal supplied to an input terminal, to generate a clock signal with a front edge part delayed by a predetermined time. Each delay circuit further generates a rear edge part of the clock signal output therefrom in response to an inverted clock signal that is an inversion of a logic level of a clock signal output from the subsequent delay circuit.
