A test circuit includes a control circuit that tests a memory having a plurality of data holding circuits holding data, a plurality of write ports, and a plurality of read ports, a write port selection circuit that selects any one of the plurality of write ports based on the write port identification information identifying any one of the plurality of write ports; and a read port selection circuit that selects any one of the plurality of read ports based on the read port identification information identifying any one of the plurality of read ports, wherein the control circuit sets the write port identification information and sets the read port identification information and carries out a test on the memory via the selected write port and the selected read port.
