Berke Stuart Allen,Mutnury Bhyrav M.,Sankaranarayanan Vadhiraj
申请号：
US201615206827
公开号：
US9563384(B2)
申请日:
2016.07.11
申请国别(地区):
美国
年份:
2017
代理人:
Jackson Walker L.L.P.
摘要：
A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.
