A delay circuit (3) comprises a signal generator (FF1) and a delay mean. The signal generator (FF1) comprises a terminal for receiving a trigger signal and an output (Q) for outputting a signal when receiving a trigger signal with a pre-determined characteristic. The delay mean comprises an input for receiving the signal outputted by the signal generator (FF1) and an output (OUT) for generating a signal delayed with a delay referred to the time the delay mean received the signal outputted by the signal generator (FF1).