Bell, Jr. Robert H.,Chiang Men-Chow,Hua Hong L.,Srinivas Mysore S.
申请号：
US201313767916
公开号：
US9727469(B2)
申请日:
2013.02.15
申请国别(地区):
美国
年份:
2017
代理人:
Baudino James L.
摘要：
According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.
