AYRIGNAC Renaud,RAY Vincent,DUPONT DE DINECHIN Benoît
申请号：
US201515312961
公开号：
US2017192792(A1)
申请日:
2015.04.27
申请国别(地区):
美国
年份:
2017
代理人:
摘要：
A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.
