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MULTI-CHIP PACKAGE STRUCTURE, WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF
专利权人:
ChipMOS Technologies Inc.
发明人:
Chou Shih-Wen
申请号:
US201715484056
公开号:
US2017221860(A1)
申请日:
2017.04.10
申请国别(地区):
美国
年份:
2017
代理人:
摘要:
A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

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