Ray Joydeep,George Varghese,Sodhi Inder M.,Wilcox Jeffrey R.
申请号：
US201715427880
公开号：
US2017147214(A1)
申请日:
2017.02.08
申请国别(地区):
美国
年份:
2017
代理人:
摘要：
A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.
