Disclosed is a computer system of a heterogeneous hybrid memory architecture (10), comprising a memory unit (100), a non-volatile memory unit (200) and a BIOS unit, wherein the memory unit (100) comprises a first SPD chip (110) and accesses the computer system via a DIMM interface, and the first SPD chip (110) comprises memory capacity information about the memory unit (100); the non-volatile memory unit (200) comprises a second SPD chip (230) and accesses the computer system via a DIMM interface, and the second SPD chip (230) comprises memory capacity and memory type information about the non-volatile memory unit (200); the BIOS unit (300) is used for acquiring capacity information about the second SPD chip (230) at a power on self-test stage and then forming a system memory report by the capacity information about the second SPD chip and the memory capacity information about the memory unit (100). Also disclosed are a control method for the computer system (10) and a memory detection system (30) in the comp
