A system comprising: a switched capacitor circuit comprising a plurality of voltage divider circuit stages including a first voltage divider circuit stage coupled to a second voltage divider circuit stage; and a controller configured to supply a clock signal to the first voltage divider circuit stage to provide a first voltage on an output node of the first voltage divider circuit stage during a first half cycle of the clock signal, and a second voltage on said output node during a second half cycle of the clock signal. The second voltage divider circuit stage is configured to charge to an input voltage during a half cycle of the clock signal, and the controller is configured to synchronize charging of the second voltage divider circuit stage to a selected one of (i) the first half cycle of the clock signal, wherein the first voltage is supplied as said input voltage, and (ii) the second half cycle of the clock signal, wherein the second voltage is supplied as said input voltage.
