An integrated circuit may be provided with a specialized processing block that performs floating-point addition and subtraction operations. For this purpose, the specialized processing block includes a fused adder and subtractor stage with an adder circuit and a subtractor circuit. The adder and subtractor circuits share an alignment stage for aligning the mantissas of incoming floating-point numbers and provide a simplified normalization stage with one right shifter and one left shifter. The specialized processing blocks may be arranged in rows or columns such that an input of a first specialized processing block is directly coupled to an output of a second specialized processing block and an input of the second specialized processing block is directly coupled to an output of the first specialized processing block.
