According to various embodiments, there is provided a memory device including at least one sense amplifier having a first side and a second side, wherein the second side opposes the first side; a first array including a plurality of memory cells arranged at the first side; a second array including a plurality of memory cells arranged at the second side; a first row including a plurality of mid-point reference units arranged at the first side; and a second row including a plurality of mid-point reference units arranged at the second side, wherein each mid-point reference unit of the first row is configured to generate a first reference voltage, and wherein each mid-point reference unit of the second row is configured to generate a second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the first array based on the second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the second arra
