A three-dimensional VLSI integrated circuit apparatus is disclosed having a plurality of VLSI layers. A first VLSI layer includes a first silicon sublayer coupleable to at least one heat sink, and a first active silicon sublayer having a (first) plurality of photonic receivers (or transceivers); and a second VLSI layer including a second silicon sublayer having a first plurality of microfluidic cooling channels, and a second active silicon sublayer of the plurality of second VLSI sublayers having an interconnection network. Additional VLSI layers may also include a third VLSI layer having a third silicon sublayer having a second plurality of microfluidic cooling channels and a third active silicon sublayer having a (second) plurality of photonic transmitters (or transceivers). Additional VLSI layers may also include a third VLSI layer having microfluidic cooling channels and memory circuits, and a fourth VLSI layer having microfluidic cooling channels and parallel processing circuitry.
