A clock generator comprises a voltage controlled oscillator including a ring oscillator which has a plurality of differential inverter circuits connected in a ring shape, and a phase controller to control an output of a differential inverter circuit which belongs to a second group, in a first state or a second state, for a predetermined time period. The differential inverter circuit which belongs to the second group is distinct from a differential inverter circuit which belongs to a first group. The differential inverter circuit which belongs to the second group, in the first state, outputs a first logic signal from a first differential output terminal and outputs a second logic signal from a second differential output terminal. Further, the differential inverter circuit which belongs to the second group, in the second state, outputs the second logic signal from the first differential output terminal and outputs the first logic signal from the second differential output terminal.
