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SCAN TEST CIRCUIT, SCAN TEST METHOD, AND METHOD OF DESIGNING SCAN TEST CIRCUIT
专利权人:
MegaChips Corporation
发明人:
Nakamura Hiroyuki
申请号:
US201715411259
公开号:
US2017205463(A1)
申请日:
2017.01.20
申请国别(地区):
美国
年份:
2017
代理人:
摘要:
A scan test circuit includes a scan chain formed of a plurality of sub-scan chains, an input distribution circuit, and an output compression circuit. With the use of a bypass circuit, a plurality of sub-scan chains are formed in a compression scan mode by connecting scan cell circuits of a high confidentiality-requiring circuit among a plurality of scan cell circuits included in an internal circuit, and a plurality of sub-scan chains are formed in a non-compression scan mode by bypassing the scan cell circuits of the high confidentiality-requiring circuit.
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

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