Anderson Brent A.,Kanakasabapathy Sivananda K.,Shearer Jeffrey C.,Sieg Stuart A.,Sporre John R.,Wang Junli
申请号：
US201615197996
公开号：
US9882048(B2)
申请日:
2016.06.30
申请国别(地区):
美国
年份:
2018
代理人:
Cantor Colburn LLP `Alexanian Vazken
摘要：
A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
