Integrated circuit for use in e.g. flash memory of electronic apparatus, has resistive storage element coupled with buried-gate-selector transistor, where information is accumulated on base of specific resistance of storage element
The circuit has a storage cell including a buried-gate-selector transistor and a resistive storage element (100) that is coupled with the buried-gate-selector transistor. Resistive storage element information is accumulated on base of specific resistance of the resistive storage element. A recess is formed in an active region of the substrate, where the active region includes a source region and a drain region. The recess is arranged between the source region and the drain region, and covers a gate-oxide-layer. The resistive storage element includes a transient metal-oxide material. An independent claim is also included for a method for producing an integrated circuit.
