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Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation compensation circuit, variation measurement method, and variation compensation method
专利权人:
JAPAN SCIENCE AND TECHNOLOGY AGENCY
发明人:
Onodera Hidetoshi,Mahfuzul Islam A. K. M
申请号:
US201414913309
公开号:
US9899993(B2)
申请日:
2014.07.29
申请国别(地区):
美国
年份:
2018
代理人:
Baker & Hostetler LLP
摘要:
A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

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