A frequency division correction circuit includes: a first frequency divider (302) configured to perform decimal frequency division (divide by 1.5) on an input signal and output a first frequency division signal (CK11) and a second frequency division signal (CK14) which are different from each other in duty ratio; and a corrector (303) configured to generate a first output signal (CK21) having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.
