MOFIDI Mahbod,LOPELLI Emanuele,WIKLUND Magnus Olov,WANG Charles
申请号：
US201615163480
公开号：
US2017134030(A1)
申请日:
2016.05.24
申请国别(地区):
美国
年份:
2017
代理人:
摘要：
Disclosed are methods and apparatuses for reducing fractional spurs in an All-Digital Phase Lock Loop (ADPLL). An exemplary apparatus includes a crystal oscillator configured to generate a first frequency reference signal, a non-integer divider coupled to the crystal oscillator and configured to divide the first frequency reference signal by a non-integer variable to generate a second frequency reference signal, and a multiplexor coupled to the non-integer divider and the crystal oscillator and configured to output the first frequency reference signal or the second frequency reference signal to the ADPLL, wherein the multiplexor is configured to output the second frequency reference signal based on the ADPLL being tuned to a low fractionality channel.
