A memory system includes a control block, an antifuse voltage generator, an array voltage generator, and a memory array. The control block is used to output control signals to the memory array according to a memory control data signal. The antifuse voltage generator is used to output an antifuse control signal to the memory array according to a control signal and a driving voltage. The array voltage generator is used to output a selection signal and a following control signal to the memory array according a control signal. The memory array is coupled to the control block, the antifuse voltage generator, and the array voltage generator and configured to access data according to the first control signal, the antifuse control signal, the selection signal, and the following control signal. The first control signal comprises address information of the memory array.
