A memory device includes a first string including first and second memory cells, first and second select transistors, and a third select transistor between the first and second select transistors, a second string including third and fourth memory cells, fourth and fifth select transistors, and a sixth select transistor between the fourth and fifth select transistors, and a controller. During a first read phase, a first voltage is applied to first, second, and third select transistors, and one of fourth and fifth select transistor, and a second voltage lower than the first voltage is applied to sixth select transistor and other of fourth and fifth select transistors. During a second read phase, the second voltage is applied to fourth, fifth, and sixth select transistors, and a read target voltage is applied to a selected word line.
