A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.
