Lo Chih-Yen,Kwai Ding-Ming,Yang Chi-Chun,Wu Kuan-Te,Yu Yun-Chao,Li Jin-Fu
申请号：
US201414578053
公开号：
US9588717(B2)
申请日:
2014.12.19
申请国别(地区):
美国
年份:
2017
代理人:
Muncy, Geissler, Olds & Lowe, P.C.
摘要：
A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, μ data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<μ
