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Processor architecture using a RISC processor and multiple adjunct processors
专利权人:
MYTH INNOVATIONS, INC.
发明人:
Luckett, Jr. James Albert,Rowlee Chad Michael,Fu Shengli
申请号:
US201414547947
公开号:
US9594486(B2)
申请日:
2014.11.19
申请国别(地区):
美国
年份:
2017
代理人:
Jackson Walker LLP `Rourk Christopher J.
摘要:
A method for processing data comprising activating a reduced instruction set processor. Activating a basic input output system of the reduced instruction set processor. Activating a multiple boot loader of the reduced instruction set processor after the basic input output system has been activated. Activating a hardware abstraction layer of the reduced instruction set processor after the multiple boot loader has been activated. Activating a plurality of processors coupled to the reduced instruction set processor. Activating a common language infrastructure of the reduced instruction set processor. Synchronizing a dynamic link library of each of the plurality of processors with a common language infrastructure of the reduced instruction set processor.
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中国工程科技知识中心
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