您的位置: 首页 > 农业专利 > 详情页

Apparatus and method to optimize STT-MRAM size and write error rate
专利权人:
Intel Corporation
发明人:
Manipatruni Sasikanth,Nikonov Dmitri E.,Young Ian A.
申请号:
US201314913676
公开号:
US9711215(B2)
申请日:
2013.09.27
申请国别(地区):
美国
年份:
2017
代理人:
Blakely, Sokoloff, Taylor & Zafman LLP
摘要:
Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

意 见 箱

匿名:登录

个人用户登录

找回密码

第三方账号登录

忘记密码

个人用户注册

必须为有效邮箱
6~16位数字与字母组合
6~16位数字与字母组合
请输入正确的手机号码

信息补充