A phase detection circuit includes: a first circuit configured to generate a first phase detection signal that indicates a result of sampling a first clock signal at a transition timing of an input data signal; a second circuit configured to generate a second phase detection signal that indicates a result of sampling a second clock signal at the transition timing of the input data signal, a phase of the second clock signal being different from a phase of the first clock signal; and a third circuit configured to generate a third phase detection signal that indicates a phase of the first clock signal with respect to the input data signal based on the first phase detection signal and the second phase detection signal.
