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可変容量回路、可変容量デバイス、及びそれを用いた共振回路、通信装置
专利权人:
デクセリアルズ株式会社
发明人:
管野 正喜
申请号:
JP20150530668
公开号:
JP6262235(B2)
申请日:
2014.05.28
申请国别(地区):
日本
年份:
2018
代理人:
摘要:
The present invention achieves a proper balance among multiple constituent bias resistors of a variable-capacitance circuit by using different resistance values for resistors located at specific positions and the other resistors, thereby reducing a response time while sufficiently blocking an alternating-current component. This variable-capacitance circuit is a variable-capacitance circuit for which variable-capacitance components (C1-C4), the capacitances of which change in accordance with a control voltage, are connected in series between terminals to which an alternating-current signal is applied, and multiple bias application paths for applying a bias voltage to each of the variable-capacitance components via resistance components (R1-R5) are formed, wherein, among resistance components (R1-R5), resistance components (R1, R5) connected to the terminals, to which the alternating current is applied, have different resistance values from the resistance values of the other resistance components (R2-R4).
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

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