PROBLEM TO BE SOLVED: To provide a clock phase shift circuit that can reduce a quantization error between a phase shift amount of an output clock and an ideal phase shift amount even if a frequency-modulated input clock is input.SOLUTION: The clock phase shift circuit includes: a period measurement circuit for counting a clock number of an oscillation clock generated by a ring oscillator comprising in a predetermined number of connected stages delay cells that are the same as delay cells constituting a delay line, for a measurement period over predetermined periods of an input clock, and outputting the count value; and a first error correction circuit for generating, with the count value as a phase shift mount for an operation period tn of the input clock, an interpolation phase shift amount interpolated between the phase shift amount for the operation period tn and a phase shift amount for an operation period tn-1, and selectively outputting the phase shift mount for the operation period tn or the interpolat
