您的位置: 首页 > 农业专利 > 详情页

Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit
专利权人:
XILINX, INC.
发明人:
Gaide Brian C.
申请号:
US201514728741
公开号:
US9559669(B1)
申请日:
2015.06.02
申请国别(地区):
美国
年份:
2017
代理人:
King John J.
摘要:
A circuit for generating clock signals enabling the latching of data is described. The circuit comprises a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a latch circuit coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal; wherein a pulse width of the output clock signal is determined by the feedback signal and the input signal coupled to the pulse generator. A method of generating clock signals enabling the latching of data is also described.
来源网站:
中国工程科技知识中心
来源网址:
http://www.ckcest.cn/home/

意 见 箱

匿名:登录

个人用户登录

找回密码

第三方账号登录

忘记密码

个人用户注册

必须为有效邮箱
6~16位数字与字母组合
6~16位数字与字母组合
请输入正确的手机号码

信息补充