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PHASE DETECTION IN AN ANALOG CLOCK DATA RECOVERY CIRCUIT WITH DECISION FEEDBACK EQUALIZATION
专利权人:
Altera Corporation
发明人:
JIN, Wenyi,REN, Jihong,LEE, Hae-Chang
申请号:
EP20160174580
公开号:
EP3107239(A1)
申请日:
2016.06.15
申请国别(地区):
欧洲专利局
年份:
2016
代理人:
摘要:
An embodiment of the invention relates to a method of phase detection in a receiver circuit (100) with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap (H1) of the decision feedback equalizer (112) is separated from the feedback of the remaining plurality of taps (H2, H3, ...). The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.
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