Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current.揭示可程式化定時器電路。一個定時器電路可包括：一參考電路，其經組態以產生一偏壓電流；一電流控制振盪器，其經組態以接收該偏壓電流；及一分頻器網路，其經組態以劃分該振盪器之一輸出。該定時器電路可能夠在使用小於5nA之靜態電流的同時定時達24小時之期間。
