PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR

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专利权人:

Hyperion Core, Inc.

发明人:

VORBACH Martin

申请号：

US201615130852

公开号：

US2016306631(A1)

申请日:

2016.04.15

申请国别(地区):

美国

年份:

2016

代理人:

摘要：

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

来源网站：

中国工程科技知识中心

来源网址：

http://www.ckcest.cn/home/