Parris Patrice M.,Chen Weize,De Souza Richard J.,Hoque Md M.,McKenna John M.
申请号：
US201715427846
公开号：
US9964516(B2)
申请日:
2017.02.08
申请国别(地区):
美国
年份:
2018
代理人:
摘要：
An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
