NORTHWESTERN UNIVERSITY ;REGENTS OF THE UNIVERSITY OF MINNESOTA
发明人:
Hersam Mark C.,Geier Michael L.,Prabhumirashi Pradyumna L.,Xu Weichao,Kim Hyungil
申请号：
US201715437060
公开号：
US2017162628(A1)
申请日:
2017.02.20
申请国别(地区):
美国
年份:
2017
代理人:
摘要：
A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.
