In the present invention, a logical block of an FPGA 56 is configured by a serial communication unit 100, a serial communication control portion 101, an EEPROM controller 102, an abnormal signal processing portion 103, an LED controller 104, an operation mode controller 105, a DPRAM 106, a clutch signal input portion 107, a jig substrate input output portion 108, a RAM 109, a motor controller 110, a motor drive waveform generating portion 111, an RL (right and left) motor current F/B portion 112, a UD (up and down) motor current F/B portion 113, a potentiometer control portion 114, a thermistor control portion 115, an RL encoder control portion 116, a UD encoder control portion 117, and an FPGA block abnormality monitoring portion 118. With the above described configuration, it is possible to continue a bending operation even when a trouble occurs in a part of functions of the bending control portion.
